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Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Microsoft's silicon development teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Opportunities within our silicon teams represent a variety of disciplines including, but not limited to, architecture, design, verification, performance modeling, and physical design supporting the development of custom silicon. We are looking for you to bring your authentic self to help us in designing for the future!

As the Princpal Memory Hierarchy Architect in the silicon engineering organization, you will be a member of the team responsible for defining the overall SoC Architecture. You will work closely with the product and platform architecture teams, peer System on Chip (SoC) architects, IP architects, Performance/Modeling architects, Software (OS and Hypervisor) and Firmware architects, Design, Validation, and Execution teams, etc. to ensure our SOC and IPs enable performant, efficient, and industry-leading systems. The team you’ll be part of will be involved in numerous projects within Microsoft, developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

• Memory technology roadmaps including, but not limited to: DDR, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM/MRDIMM, and emerging memory technologies

• Defining/driving the overall SoC memory hierarchy architecture from L3, L4, Main Memory, Memory Expansion, IO caching, and exploring alternative caching hierarchy/architectures

• Defining and driving the overall end-to-end Memory Hierarchy Quality of Service (QoS) architecture and microarchitecture (where appropriate) across hardware, software, and firmware

• Working closely with performance architects to define and drive modeling methodologies to enable memory hierarchy and QoS performance analysis and evaluation

• Working closely with memory controller architects and micro-architects to productize features

• Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy

• Collaborating across teams to come up with the best solution possible with a One Microsoft mindset.

• Challenging the status quo with a growth mindset to push the envelope and enable world-class SOC products across Microsoft.

Other

• Embody ourCulture (https://careers.microsoft.com/v2/global/en/culture) & Values (https://www.microsoft.com/en-us/about/corporate-values)

Qualifications

Requirements:

• 9+ years of related technical engineering experience Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science.

• 7 + years of experience in SoC memory hierarchy/architecture, and contemporary as well as emerging memory technologies.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications

• Understanding of I/O, memory subsystems, coherency flows, interconnect, and QoS mechanisms

• Understanding of computer architecture, SoC and system Hardware and Software architectures, and the associated tradeoffs

• Understanding of cache and memory controller architecture, micro architecture, and design

• Excellent communication, collaboration and teamwork skills and the ability to contribute to diverse and inclusive teams

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until September 2, 2024.

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .