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Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 5 years of experience with SoC Integration focused on low power design.

• Experience with new process technology based SoC integration flow development and tape-out.

• Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.

• Experience with physical design flow development and design closure for multiple ASIC/SoCs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience in System-on-a-Chip (SoC) integration, including 2.5D and 3 Dimensional Integrated Circuit integration and sign-off.

• Experience in extraction of ASIC design parameters, Quality of Results (QoR) metrics, and analyzing trends.

• Experience in co-optimization to enable schedule sensitive development with consideration of block complexity, power domains, clocking, congestion, etc.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

• Develop, support and execute SoC integration flow development and execution, including Multiple scenarios of Die Size planing, Bump planning, IO and Block placements, Power regions planning, Layout routing planning, Product Graphics grid with multiple power regions, etc.

• Be responsible for bump/micro-bump to package integration planning and implementation of package driven feedback into high-level.

• Ensure SoC integration is block friendly, easy to implement and meets Power, Performance, and Area goals.

• Ensure multiple power domains Electromigration/Voltage (EM/IR), bump planing will meet reliability requirements.

• Own and drive execution of high-level SoC and partner with foundry to resolve issues related to new technologies.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.