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Job Description

Our team develops Extraction runsets using state-of-the-art EDA tools for advanced technologies at Intel. In this role you will be working with a team of senior members and contributing towards development and support of extraction runsets (ICV-PXL/Calibre-SVRF/Pegasus), extraction flows, and validation methodologies. A successful candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with Process Development Teams, and EDA vendors is expected on a frequent basis in order enable production level extraction solutions.

Responsibilities are the following but not limited to:

Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.

Our team develops physical verification runsets using state-of-the-art EDA software tools for advanced technologies at Intel.

This is an entry level position and compensation will be given accordingly.

#DesignEnablement

Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess a BS degree with 3+ months of experience or MS degree with 6+ months of experience in Computer Science, Computer Engineering, Electrical Engineering, or related field.

6+ months of experience in the following:

• Digital/Analog design or verification, physical verification, parasitic extraction, or electronic design software development/automation.

• Unix or Linux operating system.

• Software programming skills in C++ or Python or Perl or TCL or shell.

Preferred Qualifications:

6+ months of experience in the following:

-DRC/LVS runset development or support in any of the following EDA tools.

• Cadence Pegasus and/or Quantus

• Synopsys ICV and/or StarRC

• Siemens/Mentor Calibre and/or xACT/xACT

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, TX, Austin; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $91,500.00-$137,436.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.